1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device provided with external pins for input and/or output of signals.
2. Description of the Background Art
Conventionally, a semiconductor integrated circuit device provided with a large number of external pins incorporates therein a test circuit for detecting contact failure between respective external pins and board interconnection when mounted on a board.
In a conventional testing method, a signal of an H level is applied to board interconnection, and when the signal at the H level is transmitted via an external pin to a test circuit, it is determined that the contact state of the board interconnection and the external pin is normal. When the signal at the H level is not transmitted to the test circuit via the external pin, the determination is made that the contact between the board interconnection and the external pin is defective.
When a contact resistance value between the board interconnection and the external pin is several ohms, signal transmission timing is delayed by several ten ps, thereby reducing a signal voltage by several ten mV. This poses substantially no problem on a conventional semiconductor integrated circuit device. However, it may cause a fatal problem for a high-speed device such as a DDR SDRAM (double date rate, synchronous dynamic random access memory).
Further, with such a high-speed device, an error in determination of good/defective product may occur at a test before shipment, due to the contact resistance value between the external pin and a socket of a tester.
The same problem may arise when neighboring two external pins are electrically conducted to each other at a high resistance value.
The conventional testing method would only make a digital determination whether the contact state between the external pin and the board interconnection or the socket is normal. Such method is insufficient for testing of the high-speed device.